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ltc4011 4011fb typical a pplica t ion fea t ures descrip t ion high effciency standalone nickel battery charger a pplica t ions n complete nimh/nicd charger for 1 to 16 cells n no microcontroller or firmware required n 550khz synchronous pwm current source controller n no audible noise with ceramic capacitors n powerpath? control support n programmable charge current: 5% accuracy n wide input voltage range: 4.5v to 34v n automatic trickle precharge n C?v fast charge termination n optional ?t/?t fast charge termination n automatic nimh top-off charge n programmable timer n automatic recharge n multiple status outputs n micropower shutdown n 20-lead thermally enhanced tssop package n integrated or standalone battery charger n portable instruments or consumer products n battery-powered diagnostics and control n back-up battery management l, lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. the ltc ? 4011 provides a complete, cost-effective nickel battery fast charge solution in a small package using few external components. a 550khz pwm current source controller and all necessary charge initiation, monitoring and termination control circuitry are included. the ltc4011 automatically senses the presence of a dc adapter and battery insertion or removal. heavily discharged batteries are precharged with a trickle cur - rent. the ltc4011 can simultaneously use both C? v and ?t/?t fast charge termination techniques and can detect various battery faults. if necessary, a top-off charge is automatically applied to nimh batteries after fast charg - ing is completed. the ic will also resume charging if the battery self-discharges after a full charge cycle. all ltc4011 charging operations are qualifed by actual charge time and maximum average cell voltage. charging may also be gated by minimum and maximum temperature limits. nimh or nicd fast charge termination parameters are pin-selectable. integrated powerpath control support ensures that the system remains powered at all times without allowing load transients to adversely affect charge termination. 2a nimh battery charger 2a nimh charge cycle at 1c 0.1f 10f 4.7h 10f 0.033f 0.068f fault infet chrg from adapter 5v toc ready
ltc4011 4011fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) v cc (input supply) to gnd......................... C0.3v to 36v dcin to gnd .............................................. C0.3v to 36v fault , chrg, v cell , v cdiv , sense, bat, toc or ready to gnd ........................... C0.3v to v cc + 0.3v sense to bat ........................................................0.3v chem, v temp or timer to gnd ................ C0.3v to 3.5v pgnd to gnd .........................................................0.3v operating ambient temperature range (note 2) ........................................................ 0c to 85c operating junction temperature (note 3) ............. 125c storage temperature range ...................C 65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 4) the l indicates specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 12v, bat = 4.8v, gnd = pgnd = 0v, unless otherwise noted. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v cc supply v cc input voltage range l 4.5 34 v i shdn shutdown quiescent current (note 5) v cc = bat = 4.8v 5 10 a i q quiescent current waiting to charge (pause) l 3 5 ma i cc operating current fast charge state, no gate load l 5 9 ma v uvlo undervoltage threshold voltage v cc increasing l 3.85 4.2 4.45 v v uv(hyst) undervoltage hysteresis voltage 170 mv v shdni shutdown threshold voltage dcin C v cc , dcin increasing l 5 30 60 mv v shdnd shutdown threshold voltage dcin C v cc , dcin decreasing l C60 C25 C5 mv v ce charge enable threshold voltage v cc C bat, v cc increasing l 400 510 600 mv intv dd regulator v dd output voltage no load l 4.5 5 5.5 v i dd short-circuit current (note 6) intv dd = 0v l C100 C50 C10 ma intv dd(min) output voltage v cc = 4.5v, i dd = C10ma l 3.85 v fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 dcin fault chrg chem gnd v rt v temp v cell v cdiv timer infet ready v cc tgate pgnd bgate intv dd toc bat sense 21 t jmax = 125c, ja = 38c/w exposed pad (pin 21) is gnd, must be soldered to pcb to obtain specified thermal resistance o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc4011cfe#pbf ltc4011cfe#trpbf ltc4011cfe 20-lead plastic tssop 0c to 85c lead based finish tape and reel part marking package description temperature range ltc4011cfe ltc4011cfe#tr ltc4011cfe 20-lead plastic tssop 0c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc4011 4011fb e lec t rical c harac t eris t ics symbol parameter conditions min typ max units thermistor termination v rt output voltage r l = 10k l 3.075 3 3.3 3.525 3.6 v v i rt short-circuit current v rt = 0v l C9 C1 ma pwm current source v fs bat C sense full-scale regulation voltage (fast charge) 0.3v < bat < v cc C 0.3v (note 5) bat = 4.8v l 95 95 100 100 105 105 mv mv v pc bat C sense precharge regulation voltage 0.3v < bat < v cc C 0.3v (note 5) bat = 4.8v l 16 16 20 20 24 24 mv mv v tc bat C sense top-off charge regulation voltage 0.3v < bat < v cc C 0.3v (note 5) bat = 4.8v l 6.5 6.5 10 10 13.5 13.5 mv mv ?v li bat C sense line regulation 5.5v < v cc < 25v, fast charge 0.3 mv i bat bat input bias current 0.3v < bat < v cc C 0.1v C2 2 ma i sense sense input bias current sense = bat 50 150 a i off input bias current sense or bat, v cell = 0v l C1 0 1 a f typ typical switching frequency l 460 550 640 khz f min minimum switching frequency l 20 30 khz dc max maximum duty cycle 98 99 % v ol(tg) tgate output voltage low (v cc C tgate, note 7) v cc > 9v, no load v cc < 7v, no load l l 5 v cc C 0.5 5.6 v cc 8.75 v v v oh(tg) tgate output voltage high v cc C tgate, no load l 0 50 mv t r(tg) tgate rise time c load = 3nf, 10% to 90% 35 100 ns t f(tg) tgate fall time c load = 3nf, 10% to 90% 45 100 ns v ol(bg) bgate output voltage low no load l 0 50 mv v oh(bg) bgate output voltage high no load l intv dd C 0.075 intv dd v t r(bg) bgate rise time c load = 1.6nf, 10% to 90% 35 80 ns t f(bg) bgate fall time c load = 1.6nf, 10% to 90% 15 80 ns adc inputs i leak analog channel leakage 0v < v cell < 2v, 550mv < v temp < 2v 100 na charger thresholds v bp battery present threshold voltage l 320 350 370 mv v bov battery overvoltage l 1.815 1.95 2.085 v v mfc minimum fast charge voltage l 850 900 950 mv v fcbf fast charge battery fault voltage l 1.17 1.22 1.27 v ?v term C ? v termination chem open (nicd) chem = 0v (nimh) l l 16 6 20 10 25 14 mv mv v ar automatic recharge voltage v cell decreasing l 1.260 1.325 1.390 v ?t term ?t termination (note 8) chem = 3.3v (nicd) chem = 0v (nimh) l l 1.3 0.5 2 1 2.7 1.5 c/min c/min t min minimum charging temperature (note 8) v temp increasing l 0 5 9 c t maxi maximum charge initiation temperature (note 8) v temp decreasing, not charging l 41.5 45 47 c the l indicates specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 12v, bat = 4.8v, gnd = pgnd = 0v, unless otherwise noted.
ltc4011 4011fb symbol parameter conditions min typ max units t maxc maximum fast charge temperature (note 8) v temp decreasing, fast charge l 57 60 63 c v temp(d) v temp disable threshold voltage l 2.8 3.3 v v temp(p) pause threshold voltage l 130 280 mv charger timing ?t timer internal time base error l C10 10 % ?t max programmable timer error r timer = 49.9k l C20 20 % powerpath control v fr infet forward regulation voltage dcin C v cc l 15 55 100 mv v ol(infet) output voltage low v cc C infet, no load l 3.75 5.2 7 v v oh(infet) output voltage high v cc C infet, no load l 0 50 mv t off(infet) infet off delay time c load = 10nf, infet to 50% 3 15 s status and chemistry select v ol output voltage low (i load = 10ma) v cdiv all other status outputs l l 435 300 700 600 mv mv i lkg output leakage current all status outputs inactive, v out = v cc l C10 10 a i ih(vcdiv) input current high v cdiv = v bat (shutdown) l C1 1 a v il input voltage low chem (nimh) l 900 mv v ih input voltage high chem (nicd) l 2.85 v i il input current low chem = gnd l C20 C5 a i ih input current high chem = 3.3v l C20 20 a e lec t rical c harac t eris t ics the l indicates specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 12v, bat = 4.8v, gnd = pgnd = 0v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4011c is guaranteed to meet performance specifcations from 0c to 70c. specifcations over the 0c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: operating junction temperature t j (in c) is calculated from the ambient temperature t a and the total continuous package power dissipation p d (in watts) by the formula: t j = t a + ja ? p d refer to the applications information section for details. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may result in device degradation or failure. note 4: all current into device pins is positive. all current out of device pins is negative. all voltages are referenced to gnd, unless otherwise specifed. note 5: these limits are guaranteed by correlation to wafer level measurements. note 6: output current may be limited by internal power dissipation. refer to the applications information section for details. note 7: either tgate v oh may apply for 7.5v < v cc < 9v. note 8: these limits apply specifcally to the thermistor network shown in figure 5 in the applications information section with the values specifed for a 10k ntc ( of 3750). limits are then guaranteed by specifc v temp voltage measurements during test.
ltc4011 4011fb typical p er f or m ance c harac t eris t ics nicd charge cycle at 1c nicd charge cycle at 2c nimh charge cycle at 0.5c battery present threshold voltage (per cell) minimum fast charge threshold voltage (per cell) automatic recharge threshold voltage (per cell) battery overvoltage threshold voltage (per cell) C?v termination voltage (per cell)
ltc4011 4011fb typical p er f or m ance c harac t eris t ics programmable timer accuracy charge current accuracy charger effciency at i out = 2a charger soft-start fast charge current line regulation fast charge current output regulation pwm switching frequency infet forward regulation voltage infet off delay time
ltc4011 4011fb typical p er f or m ance c harac t eris t ics powerpath switching 100s/div current (a) current (a) shutdown quiescent current pwm input bias current (off) undervoltage lockout threshold voltage shutdown threshold voltage (dcin C v cc ) charge enable threshold voltage (v cc C bat) thermistor disable threshold voltage pause threshold voltage
ltc4011 4011fb p in func t ions dcin (pin 1): dc power sense input. the ltc4011 senses voltage on this pin to determine when an external dc power source is present. this input should be isolated from v cc by a blocking diode or powerpath fet. refer to the applications information section for complete details. operating voltage range is gnd to 34v. fault (pin 2): active-low fault indicator output. the ltc4011 indicates various battery and internal fault condi- tions by connecting this pin to gnd. refer to the operation and applications information sections for further details. this output is capable of driving an led and should be left foating if not used. fault is an open-drain output to gnd with an operating voltage range of gnd to v cc . chrg (pin 3): active-low charge indicator output. the ltc4011 indicates it is providing charge to the battery by connecting this pin to gnd. refer to the operation and applications information sections for further details. this output is capable of driving an led and should be left foating if not used. chrg is an open-drain output to gnd with an operating voltage range of gnd to v cc . chem (pin 4): battery chemistry selection input. this pin should be wired to gnd to select nimh fast charge termination parameters. if a voltage greater than 2.85v is applied to this pin, or it is left foating, nicd parameters are used. refer to the applications information section for further details. operating voltage range is gnd to 3.3v. gnd (pin 5): ground. this pin provides a single-point ground for internal references and other critical analog circuits. v rt (pin 6): thermistor network termination output. the ltc4011 provides 3.3v on this pin to drive an external thermistor network connected between v rt, v temp and gnd. additional power should not be drawn from this pin by the host application. v temp (pin 7): battery temperature input. an external thermistor network may be connected to v temp to provide temperature-based charge qualifcation and additional fast charge termination control. charging may also be paused by connecting the v temp pin to gnd. refer to the operation and applications information sections for complete details on external thermistor networks and charge control. if this pin is not used it should be wired to v rt . operating voltage range is gnd to 3.3v. v cell (pin 8): average single-cell voltage input. an exter- na l voltage divider between bat and v cdiv is attached to this pin to monitor the average single-cell voltage of the battery pack. the ltc4011 uses this information to protect against catastrophic battery overvoltage and to control the charging state. refer to the applications information section for further details on the external divider network. operating voltage range is gnd to bat. intv dd voltage intv dd short-circuit current typical p er f or m ance c harac t eris t ics
ltc4011 4011fb p in func t ions v cdiv (pin 9): average cell voltage resistor divider termi- na tion. the ltc4011 connects this pin to gnd provided the charger is not in shutdown. v cdiv is an open-drain output to gnd with an operating voltage range of gnd to bat. timer (pin 10): charge timer input. a resistor connected between timer and gnd programs charge cycle timing limits. refer to the applications information section for complete details. operating voltage range is gnd to 1v. sense (pin 11): charge current sense input. an external resistor between this input and bat is used to program charge current. refer to the applications information section for complete details on programming charge current. operating voltage ranges from (bat C 50mv) to (bat + 200mv). bat (pin 12): battery pack connection. the ltc4011 uses the voltage on this pin to control current sourced from v cc to the battery during charging. allowable operating voltage range is gnd to v cc . toc (pin 13): active-low top-off charge indicator out- put. the ltc4011 indicates the top-off charge state for nimh batteries by connecting this pin to gnd. refer to the operation and applications information sections for further details. this output is capable of driving an led and should be left foating if not used. toc is an open- drain output to gnd with an operating voltage range of gnd to v cc . intv dd (pin 14): internal 5v regulator output. this pin provides a means of bypassing the internal 5v regulator used to power the bgate output driver. typically, power should not be drawn from this pin by the application circuit. refer to the application information section for additional details. bgate (pin 15): external synchronous n-channel mosfet gate control output. this output provides gate drive to an optional external nmos power transistor switch used for synchronous rectifcation to increase effciency in the step-down dc/dc converter. operating voltage is gnd to int v dd . bgate should be left foating if not used. pgnd (pin 16): power ground. this pin provides a return for switching currents generated by internal ltc4011 cir- cuits. externally , pgnd and gnd should be wired together using a very low impedance connection. refer to pcb layout considerations in the applications information section for additional grounding details. tgate (pin 17): external p-channel mosfet gate control output. this output provides gate drive to an external pmos power transistor switch used in the dc/dc converter. op - erating voltage range varies as a function of v cc . refer to the electrical characteristics table for specifc voltages. v cc (pin 18): power input. external powerpath control circuits normally connect either the dc input power sup- ply or the battery to this pin. refer to the applications information section for further details. suggested applied voltage range is gnd to 34v. ready (pin 19): active-low ready-to-charge output. the ltc4011 connects this pin to gnd if proper operating voltages for charging are present. refer to the operation section for complete details on charge qualifcation. this output is capable of driving an led and should be left foating if not used. ready is an open-drain output to gnd with an operating voltage range of gnd to v cc . infet (pin 20): powerpath control output. for very low dropout applications, this output may be used to drive the gate of an input pmos pass transistor connected between the dc input (dcin) and the raw system supply rail (v cc ). infet is internally clamped about 6v below v cc . maximum operating voltage is v cc . infet should be left foating if not used. exposed pad (pin 21): this pin provides enhanced thermal properties for the tssop. it must be soldered to the pcb copper ground to obtain optimum thermal performance.
ltc4011 0 4011fb b lock diagra m 7 8 13 14 charger state control logic thermistor interface a/d converter battery detector voltage regulator uvlo and shutdown pwm fet diode charge timer voltage reference internal voltage regulator v temp 6 v rt 4 chem 3 chrg 2 fault 1 12 11 15 16 17 dcin 5 gnd v cell 10 timer 9 v cdiv toc intv dd 4011 bd sense bat pgnd 19 ready infet v cc bgate tgate 20 18
ltc4011 4011fb o pera t ion figure 1. ltc4011 state diagram
ltc4011 4011fb o pera t ion shutdown state the ltc4011 remains in micropower shutdown until dcin (pin 1) is driven above v cc (pin 18). in shutdown all status and pwm outputs and internally generated terminations or supply voltages are inactive. current consumption from v cc and bat is reduced to a very low level. charge qualifcation state once dcin is greater than v cc , the ltc4011 exits micropower shutdown, enables its own internal supplies, provides v rt voltage for temperature sensing, and switches v cdiv to gnd to allow measurement of the average single- cell voltage. the ic also verifes that v cc is at or above 4.2v, v cc is 510mv above bat and v cell is between 350mv and 1.95v. if v cell is below 350mv, no charging will occur, and if v cell is above 1.95v, the fault state is entered, which is described in more detail below. once adequate voltage conditions exist for charging, ready is asserted. if the voltage between v temp and gnd is below 200mv, the ltc4011 is paused. if v temp is above 200mv but below 2.85v, the ltc4011 verifes that the sensed temperature is between 5c and 45c. if these temperature limits are not met or if its own die temperature is too high, the ltc4011 will indicate a fault and not al low charging to begin. if v temp is greater than 2.85v, battery temperature related charge qualifcation, monitoring and termination are disabled. once charging is fully qualifed, precharge begins (unless the ltc4011 is paused). in that case, the v temp pin is monitored for further control. the charge status indicators and pwm outputs remain inactive until charging begins. charge monitoring the ltc4011 continues to monitor important voltage and temperature parameters during all charging states. if the dc input is removed, charging stops and the shutdown state is entered. if v cc drops below 4.25v or v cell drops below 350mv, charging stops and the ltc4011 returns to the charge qualifcation state. if v cell exceeds 1.95v, charging stops and the ic enters the fault state. if an external thermistor indicates sensed temperature is beyond a range of 5c to 60c, or the internal die temperature exceeds an internal thermal limit, charging is suspended, the charge timer is paused and the ltc4011 indicates a fault condition. normal charging resumes from the previous state when the sensed temperature returns to a satisfactory range. in addition, other battery faults are detected during specifc charging states as described below. precharge state if the initial voltage on v cell is below 900mv, the ltc4011 enters the precharge state and enables the pwm current source to trickle charge using one-ffth the programmed charge current. the chrg status output is active during precharge. the precharge state duration is limited to t max /12 minutes, where t max is the maximum fast charge period programmed with the timer pin. if suffcient v cell voltage cannot be developed in this length of time, the fault state is entered, otherwise fast charge begins. fast charge state if adequate average single-cell voltage exists, the ltc4011 enters the fast charge state and begins charging at the programmed current set by the external current sense resistor connected between the sense and ba t pins. the chrg status output is active during fast charge. if v cell is initially above 1.325v, voltage-based termination processing begins immediately. otherwise C?v termination is disabled for a stabilization period of t max /12. in that case, the ltc4011 makes another fault check at t max /12, requiring the average cell voltage to be above 1.22v. this ensures the battery pack is accepting a fast charge. if v cell is not above this voltage threshold, the fault state is entered. fast charge state duration is limited to t max and the fault state is entered if this limit is exceeded. charge termination fast charge termination parameters are de pendent upon the battery chemistry selected with the chem pin. voltage- based termination (C?v) is always active after the initial voltage stabilization period. if an external thermistor network is present, chemistry-specifc limits for ?t/?t (rate of tem - p e rature rise) are also used in the termination algorithm. temperature-based termination, if enabled, becomes active as soon as the fast charge state is entered. successful charge termination requires a charge rate between c/2 and 2c. lower rates may not produce the battery voltage and temperature profle required for charge termination. (refer to figure 1)
ltc4011 4011fb o pera t ion top-off charge state if nimh fast charge termination occurs because the ?t/?t limit is exceeded after an initial period of t max /12 has expired, the ltc4011 enters the top-off charge state. top-off charge is implemented by sourcing one-tenth the programmed charge current for t max /3 minutes to ensure that 100% charge has been delivered to the battery. the chrg and toc status outputs are active during the top-off state. if nicd cells have been selected with the chem pin, the ltc4011 never enters the top-off state. automatic recharge state once charging is complete, the automatic recharge state is entered to address the self-discharge characteristics of nickel chemistry cells. the charge status outputs are inactive during automatic recharge, but v cdiv remains switched to gnd to monitor the average cell voltage. if the v cell voltage drops below 1.325v without falling below 350mv, the charge timer is reset and a new fast charge cycle is initiated. the internal termination algorithms of the ltc4011 are adjusted when a fast charge cycle is initiated from auto - matic recharge, because the battery should be almost fully charged. voltage-based termination is enabled immediately and the nimh ?t/?t limit is fxed at a battery temperature rise of 1c/minute. fault state as discussed previously, the ltc4011 enters the fault state based on detection of invalid battery voltages during vari - ous charging phases. the ic also monitors the regulation of the pwm control loop and will enter the fault state if this is not within acceptable limits. once in the fault state, the battery must be removed or dc input power must be cycled in order to initiate further charging. in the fault state, the fault output is active, the ready output is inactive, charging stops and the charge indicator outputs are inactive. the v cdiv output remains connected to gnd to allow detection of battery removal. note that the ltc4011 also uses the fault output to indi- cate that charging is suspended due to invalid battery or internal die temperatures. however, the ic does not enter the fault state in these cases and normal operation will resume when all temperatures return to acceptable levels. refer to the status outputs section for more detail. insertion and removal of batteries the ltc4011 automatically senses the insertion or removal of a battery by monitoring the v cell pin voltage. should this voltage fall below 350mv, the ic considers the bat- ter y to be absent. removing and then inserting a battery causes the ltc4011 to initiate a completely new charge cycle beginning with charge qualifcation. external pause control after charging is initiated, the v temp pin may be used to pause operation at any time. when the voltage between v temp and gnd drops below 200mv, the charge timer pauses, fast charge termination algorithms are inhibited and the pwm outputs are disabled. the status and v cdiv outputs all remain active. normal function is fully restored from the previous state when pause ends. status outputs the ltc4011 open-drain status outputs provide valuable information about the ics operating state and can be used for a variety of purposes in applications. table 1 summarizes the state of the four status outputs and the v cdiv pin as a function of ltc4011 operation. the status outputs can directly drive current-limited leds terminated to the dc input. the v cdiv column in table 1is strictly informational. v cdiv should only be used for the v cell resistor divider, as previously discussed. table 1. ltc4011 status pins ready fault chrg toc v cdiv charger state off off off off off off on off off off on ready to charge (v temp held low) or automatic recharge on off on off on precharge or fast charge (may be paused) on off on on on nimh top-off charge (may be paused) on on on o r off on or off on temperature limits exceeded off on off off on fault state (latched)
ltc4011 4011fb o pera t ion 12 ? + cc ea i th i prog r3 q pwm clock s r r4 r1 bat 11 sense r sense 15 bgate 17 tgate ltc4011 v cc p n r2 4011 f02 figure 2. ltc4011 pwm control loop pwm current source controller an integral part of the ltc4011 is the pwm current source controller. the charger uses a synchronous step-down architecture to produce high effciency and limited thermal dissipation. the nominal operating frequency of 550khz allows use of a smaller external flter components. the tgate and bgate outputs have internally clamped volt - age swings. they source peak currents tailored to smaller surface-mount power fets likely to appear in applications providing an average charge current of 3a or less. during the various charging states, the ltc4011 uses the pwm controller to regulate an average voltage between sense and bat that ranges from 10mv to 100mv. a conceptual diagram of the ltc4011 pwm control loop is shown in figure 2. the voltage across the external current programming resistor r sense is averaged by integrating error amplifer ea. an internal programming current is also pulled from input resistor r1. the i prog ? r1 product establishes the desired average voltage drop across r sense , and hence, the average current through r sense . the i th output of the error amplifer is a scaled control current for the input of the pwm comparator cc. the i th ? r3 product sets a peak current threshold for cc such that the desired aver- age current through r sense is maintained. the current comparator output does this by switching the state of the sr latch at the appropriate time. at the beginning of each oscillator cycle, the pwm clock sets the sr latch and the external p -channel mosfet is switched on (n -channel mosfet switched off) to refresh the current carried by the external inductor. the inductor current and voltage drop across r sense begin to rise linearly. during normal operation, the pfet is turned off (nfet on) during the cycle by cc when the voltage difference across r sense reaches the peak value set by the output of ea. the inductor current then ramps down linearly until the next rising pwm clock edge. this closes the loop and maintains the desired average charge current in the external inductor. low dropout charging after charging is initiated, the ltc4011 does not require that v cc remain at least 500mv above bat because situ- ations exist where low dropout charging might occur. in one instance, parasitic series resistance may limit pwm headroom (between v cc and bat) as 100% charge is reached. a second case can arise when the dc adapter selected by the end user is not capable of delivering the current programmed by r sense , causing the output volt- age of the adapter to collapse. while in low dropout, the ltc4011 pwm runs near 100% duty cycle with a frequency that may not be constant and can be less than 550khz. the charge current will drop below the programmed value to avoid generating audible noise, so the actual charge delivered to the battery may depend primarily on the ltc4011 charge timer. internal die temperature the ltc4011 provides internal overtemperature detection to protect against electrical overstress, primarily at the fet driver outputs. if the die temperature rises above this thermal limit, the ltc4011 stops switching and indicates a fault as previously discussed.
ltc4011 4011fb a pplica t ions i n f or m a t ion external dc source the external dc power source should be connected to the charging system and the v cc pin through either a power diode or p-channel mosfet. this prevents catastrophic system damage in the event of an input short to ground or reverse-voltage polarity at the dc input. the ltc4011 auto - ma tically senses when this input is present. the open-circuit voltage of the dc source should be between 4.5v and 34v, depending on the number of cells being charged. in order to avoid low dropout operation, ensure 100% capacity at charge termination, and allow reliable detection of ba ttery insertion, removal or overvoltage, the following equation can be used to determine the minimum full-load voltage that should be provided by the external dc power source. dcin(min) = (n ? 2v) + 0.3v where n is the number of series cells in the battery pack. the ltc4011 will properly charge over a wide range of dcin and bat voltage combinations. operating the ltc4011 in low dropout or with dcin much greater than bat will force the pwm frequency to be much less than 550khz. the ltc4011 disables charging and sets a fault if a large dcin to bat differential would cause generation of audible noise. powerpath control proper powerpath control is an important consideration when fast charging nickel cells. this control ensures that the system load remains powered at all times, but that normal system operation and associated load transients do not adversely affect fast charge termination. for high effciency and low dropout applications, the ltc4011 can provide gate drive from the infet pin directly to an input p-channel mosfet. the battery should also be connected to the raw system supply by a switch that selects the battery for system power only if an external dc source is not present. again, for applications requiring higher effciency , a p-channel mosfet with its gate driven from the dc input can be used to perform this switching function (see figure 8). gate voltage clamping may be necessary on an external pmos transistor used in this manner at higher input voltages. alternatively, a diode can be used in place of this fet. battery chemistry selection the desired battery chemistry is selected by programming the chem pin to the proper voltage. if it is wired to gnd, a set of parameters specifc to charging nimh cells is selected. when chem is left foating or connected to v rt , charging is optimized for nicd cells. the various charging parameters are detailed in table 2. programming charge current charge current is programmed using the following equation: r mv i sense prog = 100 r sense is an external resistor connected between the sense and bat pins. a 1% resistor with a low temperature coeffcient and suffcient power dissipation capability to avoid self-heating effects is recommended. charge rate should be between approximately c/2 and 2c. inductor value selection for many applications, 10h represents an optimum value for the inductor the pwm uses to generate charge current. for applications with i prog of 1.5a or greater running from an external dc source of 15v or less, values between 5h and 7.5h can often be selected. for wider operating conditions the following equation can be used as a guide for selecting the minimum inductor value. l > 6.5 ? 10 C6 ? v dcin ? r sense , l 4.7h actual part selection should account for both manufacturing tolerance and temperature coeffcient to ensure this mini - mum. a good initial selection can be made by multiplying the calculated minimum by 1.4 and rounding up or down to the nearest standard inductance value. ultimately, there is no substitute for bench evaluation of the selected inductor in the target application, which can also be affected by other environmental factors such as ambient operating temperature. using inductor values lower than recommended by the equation shown above can result in a fault condition at the start of precharge or top-off charge.
ltc4011 4011fb programming maximum charge times connecting the appropriate resistor between the timer pin and gnd programs the maximum duration of various charging states. to some degree, the value should refect how closely the programmed charge current matches the 1c rate of targeted battery packs. the maximum fast charge period is determined by the following equation: some typical timing values are detailed in table 3. r timer should not be less than 15k. the actual time limits used by the ltc4011 have a resolution of approximately 30 seconds in addition to the tolerances given the electrical characteristics table. if the timer ends without a valid C?v or ?t/?t charge termination, the charger enters the fault state. the maximum time period is approximately 4.3 hours. cell voltage network design an external resistor network is required to provide the average single-cell voltage to the v cell pin of the ltc4011. the proper circuit for multicell packs is shown in figure 3. the ratio of r2 to r1 should be a factor of (n C 1), where n is the number of series cells in the battery pack. the value of r1 should be between 1k and 100k. this range limits the sensing error caused by v cell leakage current and prevents the on resistance of the internal nfet be- tween v cdiv and gnd from causing a signifcant error in the v cell voltage. the external resistor network is also used to detect battery insertion and removal. the flter formed by c1 and the parallel combination of r1 and r2 12 9 bat ltc4011 r2 + for two or more series cells r1 c1 r2 = r1(n ? 1) 4011 f03 v cdiv gnd 8 5 v cell figure 3. mulitple cell voltage divider a pplica t ions i n f or m a t ion table 2. ltc4011 charging parameters state chem pin bat chemistry timer t min t max i chrg termination condition pc both t max /12 5c 45c i prog /5 timer expires fc open nicd t max 5c 60c i prog C20mv per cell or 2c/minute gnd nimh t max 5c 60c i prog 1.5c/minute for first t max /12 minutes if initial v cell < 1.325v C10mv per cell or 1c/minute after t max /12 minutes or if initial v cell > 1.325v toc gnd nimh t max /3 5c 60c i prog /10 timer expires ar both 5c 45c 0 v cell < 1.325v pc: precharge fc: fast charge (initial C?v termination hold off of t max /12 minutes may apply) toc: t op-off charge (only for nimh ?t/?t fc termination after initial t max /12 period) ar: automatic recharge (temperature limits apply to state termination only) table 3. ltc4011 time limit programming examples r timer typical fast charge rate precharge limit (minutes) f ast charge vol t age stabilization (minutes) f ast charge limit (hours) top-off charge (minutes) 24.9k 2c 3.8 3.8 0.75 15 33.2k 1.5c 5 5 1 20 49.9k 1c 7.5 7.5 1.5 30 66.5k 0.75c 10 10 2 40 100k c/2 15 15 3 60
ltc4011 4011fb a pplica t ions i n f or m a t ion figure 4. single-cell monitor network 12 9 bat 10k 10k 33nf 1 cell 4011 f04 v cdiv 8 v cell where: r 0 = thermistor resistance () at t 0 t 0 = thermistor reference temperature (k) = exponential temperature coeffcient of resistance for thermistors with less than 3750, the equation for r3 yields a negative number. this number should be used to compute r2, even though r3 is replaced with a short in the actual application. an additional high temperature charge qualifcation error of between 0c and 5c may occur when using thermistors with lower than 3750. thermistors with nominal less than 3300 should be avoided. the flter formed by r4 and c1 in figure 5 is optional but recommended for rejecting pwm switching noise. alternatively, r4 may be replaced by a short, and a value chosen for c1 which will provide adequate fltering from the thevenin impedance of the remaining thermistor net - work. the flter pole frequency, which should be less than 500hz, will vary more with battery temperature without r4. external components should be chosen to make the thevenin impedance from v temp to gnd 100k or less, including r4, if present. disabling thermistor functions temperature sensing is optional in ltc4011 applications. for low cost systems where temperature sensing may not be required, the v temp pin may simply be wired to v rt to disable temperature qualifcation of all charging is recommended for rejecting pwm switching noise. the value of c1 should be chosen to yield a 1st order lowpass frequency of less than 500hz. in the case of a single cell, the external application circuit shown in figure 4 is rec - ommended to provide the necessary noise fltering and missing battery detection. thermistor network design the network for proper temperature sensing using a thermistor with a negative temperature coeffcient (ntc) is shown in figure 5. r3 is only present for thermistors with an exponential temperature coeffcient ( ) above 3750. for thermistors with below 3750, replace r3 with a short. figure 5. external ntc thermistor network 6 7 v rt r1 r2 r t r4 51k r3 c1 10nf 4011 f05 v temp the ltc4011 is designed to work best with a 5% 10k ntc thermistor with a n ear 3 750, such as the siemens/epcos b57620c103j062. in this case, the values for the external network are given by: r1 = 9.76k r2 = 28k r3 = 0 however, the ltc4011 will operate with other ntc therm - istors having different nominal values or exponential temperature coeffcients. for these thermistors, the design equations for the resistors in the external network are:
ltc4011 4011fb a pplica t ions i n f or m a t ion operations. however, this practice is not recommended for nimh cells charged well above or below their 1c rate, because fast charge termination based solely on voltage infection may not be adequate to protect the battery from a severe overcharge. a resistor between 10k and 20k may be used to connect v temp to v rt if the pause function is still desired. intv dd regulator output if bgate is left open, the intv dd pin of the ltc4011 can be used as an additional source of regulated voltage in the host system any time ready is active. switching loads on intv dd may reduce the accuracy of internal analog circuits used to monitor and terminate fast charging. in addition, dc current drawn from the intv dd pin can greatly increase internal power dissipation at elevated v cc voltages. a minimum ceramic bypass capacitor of 0.1f is recommended. calculating average power dissipation the user should ensure that the maximum rated ic junction temperature is not exceeded under all operating conditions. the thermal resistance of the ltc4011 package ( ja ) is 38c/w, provided the exposed metal pad is properly soldered to the pcb. the actual thermal resistance in the application will depend on the amount of pcb copper to which the package is soldered. feedthrough vias directly below the package that connect to inner copper layers are helpful in lowering thermal resistance. the following formula may be used to estimate the maximum average power dissipation p d (in watts) of the ltc4011 under normal operating conditions. where: i dd = average external intv dd load current, if any i vrt = load current drawn by the external thermistor network from v rt , if any q tgate = gate charge of external p-channel mosfet in coulombs q bgate = gate charge of external n-channel mosfet (if used) in coulombs v led = maximum external led forward voltage r led = external led current-limiting resistor used in the application n = number of leds driven by the ltc4011 sample applications figures 6 through 9 detail sample charger applications of various complexities. combined with the typical ap - plication on the frst page of this data sheet, these figures demonstrate some of the proper confgurations of the ltc4011. mosfet body diodes are shown in these fgures strictly for reference only. figure 6 shows a minimum application, which might be encountered in low cost nicd fast charge applications. fet-based powerpath control allows for maximum input voltage range from the dc adapter. the ltc4011 uses C ? v to terminate the fast charge state, as no external temperature information is available. nonsynchronous pwm switching is employed to reduce external component cost. a single led indicates charging status. a 3a nimh application of medium complexity is shown in figure 7. powerpath control that is completely fet-based allows for both minimum input voltage overhead and mini - m u m sw itchover loss when operating from the battery. p-channel mosfet q4 functions as a switch to connect the battery to the system load whenever the dc input adapter is removed. if the maximum battery voltage is less than the maximum rated v gs of q4, diode d1 and resistor r5 are not required. otherwise choose the zener voltage of d1 to be less than the maximum rated v gs of q4. r5 provides a bias current of (v bat C v zener )/(r5 + 20k) for d1 when the input adapter is removed. choose r5 to make this current, which is drawn from the battery, just large enough to develop the desired v gs across d1. precharge, fast charge and top-off states are indicated by external leds. the v temp thermistor network allows the ltc4011 to accurately terminate fast charge under a variety of applied charge rates. use of a synchronous pwm topol - o g y improves effciency and lowers power dissipation.
ltc4011 4011fb a pplica t ions i n f or m a t ion figure 7. 3a nimh charger with full powerpath control figure 6. minimum 1a ltc4011 application 0.1f 10f 10f 10h fault infet chrg from adapter 12v toc ready 0.033f 0.068f 20f 0.1f 4.7h 20f fault chrg toc ready from adapter 12v a full-featured 2a ltc4011 application is shown in figure 8. fet-based powerpath allows for maximum input voltage range from the dc adapter. the inherent voltage ratings of the v cell , v cdiv , sense and bat pins allow charging of one to sixteen series nickel cells in this application, governed only by the v cc overhead limits previously dis- cussed. the application includes all average cell voltage and battery temperature sensing circuitry required for the ltc4011 to utilize its full range of charge qualifcation, safety monitoring and fast charge termination features. led d1 indicates valid dc input voltage and installed battery, while leds d2 and d3 indicate charging. led d4 indicates fault conditions. the grounded chem pin selects the nimh charge termination parameter set.
ltc4011 0 4011fb a pplica t ions i n f or m a t ion figure 8. full-featured 2a ltc4011 application 0.1f d1 d2 d3 d4 10f 6.8h 10f from adapter 12v fault infet chrg toc ready figure 9. ltc4011 with mcu interface 0.1f 10f 22h nimh pack with 10k ntc (1ahr) fault chrg toc ready pause from mcu infet from adapter 24v while the ltc4011 is a complete, standalone solution, figure 9 shows that it can also be interfaced to a host microprocessor. the host mcu can control the charger directly with an open-drain i/o port connected to the v temp pin, if that port is low leakage and can tolerate at least 2v. the charger state is monitored on the four ltc4011 status outputs. charging of nimh batteries is selected in this example. however, nicd (chem v rt ) parameters could be chosen as well.
ltc4011 4011fb a pplica t ions i n f or m a t ion unlike all of the other applications discussed so far, the battery continues to power the system during charging. the mcu could be powered directly from the battery or from any type of post regulator operating from the battery. in this confguration, the ltc4011 relies expressly on the ability of the host mcu to know when load transients will be encountered. the mcu should then pause charging (and thus C?v processing) during those events to avoid premature fast charge termination. if the mpu cannot reli - ably per form this function, full powerpath control should be implemented. in most applications, there should not be an external load on the battery during charge. excessive battery load current variations, such as those generated by a post-regulating pwm, can generate suffcient voltage noise to cause the ltc4011 to prematurely terminate a charge cycle and/or prematurely restart a fast charge. in this case, it may be necessary to inhibit the ltc4011 after charging is complete until external gas gauge circuitry indicates that recharging is necessary. shutdown power is applied to the ltc4011 through the body diode of q2 in this application. waveforms sample waveforms for a standalone application during a typical charge cycle are shown in figure 10. note that these waveforms are not to scale and do not represent the complete range of possible activity. the fgure is simply intended to allow better conceptual understanding and to highlight the relative behavior of certain signals generated by the ltc4011 during a typical charge cycle. initially, the ltc4011 is in low power shutdown as the system operates from a heavily discharged battery. a dc adapter is then connected such that v cc rises above 4.25v and is 500mv above bat. the ready output is asserted when the ltc4011 completes charge qualifcation. when the ltc4011 determines charging should begin, it starts a precharge cycle because v cell is less than 900mv. as long as the temperature remains within prescribed limits, the ltc4011 charges (tgate switching), applying limited current to the battery with the pwm in order to bring the average cell voltage to 900mv. when the precharge state timer expires, the ltc4011 begins fast charge if v cell is greater than 900mv. the pwm, charge timer and internal termination control are suspended if pause is asserted (v temp < 200mv), but all status outputs continue to indicate charging is in progress. the fast charge state continues until the selected voltage or temperature termination criteria are met. figure 10 sug - gests termination based on ?t/?t, which for nimh would be an increase greater than 1c per minute. because nimh charging terminated due to ?t/?t and the fast charge cycle had lasted more than t max /12 minutes, the ltc4011 begins a top-off charge with a current of i prog /10. top-off is an internally timed charge of t max /3 minutes with the chrg and toc outputs continuously asserted. finally , the ltc4011 enters the automatic recharge state where the chrg and toc outputs are deasserted. the pwm is disabled but v cdiv remains asserted to monitor v cell . the charge timer will be reset and fast charging will resume if v cell drops below 1.325v. the ltc4011 enters shutdown when the dc adapter is removed, minimizing current draw from the battery in the absence of an input power source. while not a part of the sample waveforms of figure 10, temperature qualifcation is an ongoing part of the charg - ing process, if an external thermistor network is detected by the ltc4011. should prescribed temperature limits be exceeded during any particular charging state, charging would be suspended until the sensed temperature returned to an acceptable range. battery-controlled charging because of the programming arrangement of the ltc4011, it may be possible to confgure it f or battery-controlled charging. in this case, the battery pack is designed to provide customized information to an ltc4011-based charger, allowing a single design to service a wide range of application batteries. assume the charger is designed to provide a maximum charge current of 800ma (r sense = 125m). figure 11 shows a 4-cell nicd battery pack for which 800ma represents a 0.75c rate. when connected to the charger, this pack would provide battery tempera - ture information and correctly confgure both fast charge termination parameters and time limits for the internal nicd cells.
ltc4011 4011fb a pplica t ions i n f or m a t ion a second possibility is to confgure an ltc4011-based charger to accept battery packs with varying numbers of cells. by including r2 of the average cell voltage divider network shown in figure 3, battery-based programming of the number of series-stacked cells could be realized without defeating ltc4011 detection of battery insertion or removal. figure 12 shows a 2-cell nimh battery pack that programs the correct number of series cells when it is connected to the charger, along with indicating chemistry and providing temperature information. any of these battery pack charge control concepts could be combined in a va riety of ways to service custom application needs. charging parallel cells is not recommended. pcb layout considerations to prevent magnetic and electrical feld radiation and high frequency resonant problems, proper layout of the components connected to the ltc4011 is essential. refer to figure 13. for maximum effciency, the switch node rise and fall times should be minimized. the following pcb design priority list will help ensure proper topology. layout the pcb using this specifc order. 1. input capacitors should be placed as close as possible to switching fet supply and ground connections with the shortest copper traces possible. the switching fets must be on the same layer of copper as the input figure 11. nicd battery pack with time limit control figure 10. charging waveforms example ( pause) ready chrg toc 7 1200mahr nicd cells battery pack v temp 4 chem 10 timer nc 66.5k 4011 f11 + ? 10k ntc figure 12. nimh battery pack indicating number of cells 7 1500mahr nimh cells battery pack v temp 8 v cell r2 4 chem 4011 f12 + ? 10k ntc
ltc4011 4011fb capacitors. vias should not be used to make these connections. 2. place the ltc4011 close to the switching fet gate terminals, keeping the connecting traces short to produce clean drive signals. this rule also applies to ic supply and ground pins that connect to the switching fet source pins. the ic can be placed on the opposite side of the pcb from the switching fets. 3. place the inductor input as close as possible to the drain of the switching fets. minimize the surface area of the switch node. make the trace width the minimum needed to support the programmed charge current. use no copper flls or pours. avoid running the con - nection on multiple copper layers in parallel. minimize capacitance from the switch node to any other trace or plane. 4. place the charge current sense resistor immediately adjacent to the inductor output, and orient it such that current sense traces to the ltc4011 are short. these feedback traces need to be run together as a single pair with the smallest spacing possible on any given layer on which they are routed. locate any flter component on these traces next to the ltc4011, and not at the sense resistor location. 5. place output capacitors adjacent to the sense resisitor output and ground. 6. output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before tying back into system ground. 7. connection of switching ground to system ground, or any internal ground plane should be single-point. if the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. route analog ground as a trace tied back to the ltc4011 gnd pin before connecting to any other ground. avoid using the system ground plane. a useful cad technique is to make analog ground a separate ground net and use a 0 resistor to connect analog ground to system ground. 9. a good rule of thumb for via count in a given high current path is to use 0.5a per via. be consistent when applying this rule. 10. if possible, place all the parts listed above on the same pcb layer. 11. copper flls or pours are good for all power connec - tions except as noted above in rule 3. copper planes on multiple layers can also be used in parallel. this helps with thermal management and lowers trace in - ductance, which further improves emi performance. 12. for best current programming accuracy, provide a kelvin connection from r sense to sense and bat. see figure 14 for an example. 13. it is important to minimize parasitic capacitance on the timer, sense and bat pins. the traces connecting these pins to their respective resistors should be as short as possible. figure 13. high speed switching path 4011 f13 v bat l1 v in high frequency circulating path bat switch node c in switching ground c out d1 figure 14. kelvin sensing of charge current sense 4011 f14 direction of charging current r sense bat a pplica t ions i n f or m a t ion
ltc4011 4011fb p ackage descrip t ion fe20 (cb) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 C 6.60* (.252 C .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation cb
ltc4011 4011fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 01/10 changes to typical application updated order information section changes to electrical characteristics changes to operation section changes to applications information changes to figures 6, 7, 8, 9 1 2 2, 3, 4 12, 13, 14 15, 16, 19, 21, 22 19, 20 (revision history begins at rev b)
ltc4011 4011fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 4 34-0507 www.linear.com ? linear technology corporation 2005 lt 0110 rev b ? printed in usa part number description comments lt ? 1510 constant-voltage/constant-current battery charger up to 1.5a charge current for li-ion, nicd and nimh batteries lt1511 3a constant-voltage/constant-current battery charger high effciency, minimum external components to fast charge lithium, nimh and nicd batteries lt1513 sepic constant- or programmable-current/constant- voltage battery charger charger input voltage may be higher, equal to or lower than battery voltage, 500khz switching frequency ltc1760 smart battery system manager autonomous power management and battery charging for two smart batteries, smbus rev 1.1 compliant ltc1960 dual battery charger/selector with spi 11-bit v-dac, 0.8% voltage accuracy, 10-bit i-dac, 5% current accuracy ltc4008 high effciency, programmable voltage/current battery charger constant-current/constant-v oltage switching regulator, resistor voltage/ current programming, ac adapter current limit and thermistor sensor and indicator outputs ltc4010 high effciency standalone nickel battery charger complete nimh/nicd charger in a small 16-pin package, constant-current switching regulator ltc4060 standalone linear nimh/nicd fast charger complete nimh/nicd charger in a small leaded or leadless 16-pin package, no sense resistor or blocking diode required ltc4100 smart battery charger controller level 2 charger operates with or without mcu host, smbus rev. 1.1 compliant ltc4150 coulomb counter/battery gas gauge high side sense of charge quantity and polarity in a 10-pin msop ltc4411 2.6a low loss ideal diode no external mosfet, automatic switching between dc sources, simplifed, 140m on resistance, thinsot? package ltc4412/ ltc4412hv low loss powerpath controllers very low loss replacement for power supply oring diodes using minimal external components, 3v v in 28v, (3v v in 36v for hv) ltc4413 dual 2.6a, 2.5v to 5.5v, ideal diodes low loss replacement for oring diodes, 100m on resistance thinsot is a trademark of linear technology corporation. r ela t e d p ar t s

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